

module counter (clock, reset, StopCounter, creg0, creg1, creg2, creg3);

// ------------------------ PORT declaration ------------------------ //
input StopCounter,reset,clock;
output [7:0] creg0,creg1,creg2,creg3;

// ------------------------- Registers/Wires ------------------------ //
reg [15:0] counter;
reg isStop;

assign creg0 = 0;
assign creg1 = 0;
assign creg2 = counter[15:8];
assign creg3 = counter[7:0];

always @(posedge clock or posedge reset)
begin
	if (reset)
	begin
		counter = 0;
		isStop = 0;
	end
	else if(StopCounter)
	begin
		isStop = 1;
	end
	else if(!isStop)
	begin
		counter = counter+1;
	end
end

endmodule

